Intel’s followed up on its acquisition of Altera by baking a microprocessor into a field-programmable gate array (FPGA).
The Stratix 10 family is part of the company’s push beyond its stagnating PC-and-servers homeland into emerging markets like high-performance computing and software-defined networking.
Intel says the quad-core 64-bit ARM Cortex-A53 processor helps position the device for “high-end compute and data-intensive applications ranging from data centres, network infrastructure, cloud computing, and radar and imaging systems.”
Compared to the Stratix V, Altera’s current generation before the Chipzilla slurp, Intel says the Stratix 10 has five times the density and twice the performance; 70 per cent lower power consumption at equivalent performance; 10 Tflops (single precision); and 1 TBps memory bandwidth.
The devices will be pitched at acceleration and high-performance networking kit.
The Stratix 10 “Hyperflex architecture” uses bypassable registers – yes, they’re called “Hyper-Registers”, which are associated with individual routing segments in the chip, and are available at the inputs of “all functional blocks” like adaptive logic modules (ALMs), embedded memory blocks, and digital signal processing (DSP) blocks.
Designs can bypass individual Hyper-Registers, so design tools can automatically choose the best register location. Intel says this means “performance tuning does not require additional ALM resources … and does not require additional changes or added complexity to the design’s place-and-route.”
The company reckons the design also cuts down on on-chip routing congestion.